Input/Output in DS

Communicate between chip & external world.

  • Requirements
    • Operate at compatible voltage levels
    • Provide adequate bandwidth
    • Limit slew rates to control di/dt noise
    • Use small number of pins (low cost)

Digital System I/O

  • General-purpose digital & analog I/O pins
  • Timers
  • Serial I/O: single-bit transmission
    • Synchronous Serial Protocol (SPI)
    • UART
    • I2C, USB, Ethernet, ...
Synchronous Serial Protocol (SPI)
  • SCK: master initiate communication by sending clock pulses to slave
  • SDO: master sends data to slave (msb first)
    • Even if the master only needs to receive data from slave, it must still trigger the SPI communication by sending arbitrary bytes
  • SDI: slave sends data to master (msb first)

Universal Asynchronous RX/TX (UART)
  • Without sending a clock
    • Robust for a small frequency error and phrase difference
  • Idle: line HIGH
  • Start: detect falling transition from idle to start
  • Parity: detect bit corruption
  • Configuration
    • Start bit + 7-8 data bits + parity bit (optional) + 1+ stop bits
    • baud: symbols/sec
      • 9600 symbols/sec -> 960 characters/sec -> 7680 data bits/sec

Analog I/O
  • A/D conversion
    • Often included in microcontroller
    • $$V{ref-} - V{ref+}$$ to $$0-2^{N-1}$$
  • D/A conversion
    • Often external
    • $$0-2^{N-1}$$ to $$V{ref-} - V{ref+}$$
  • Limitation
    • Resolution
    • Dynamic range
    • Sampling rate
    • Accuracy

  • Data conversion
    • Quantization noise exists even with ideal A/D & D/A converters

Bluetooth
Personal Computer I/O
  • Universal Serial Bus (USB)
    • Standardized cables/software for peripherals
  • Peripheral Component Interconnect (PCI)
    • 32-bit parallel bus
    • Used for expansion cards
  • SATA
    • Hard drive interface
  • TCP/IP
    • Physical connection: Ethernet cable or Wi-Fi

Speed of DS

  • High-speed serial links
    • Parallel links with data bust + clock signal (most I/O)
      • Difference in delay among bus wires limits the speed of the bus
      • Bus connected to multiple devices suffer from transmission line problems
    • Point-to-point serial links
      • Data transmitted on a differential pair of wires
      • No explicit clock sent; clock recovered by watching the timing of data transitions
  • High-speed digital design
    • Broad band
      • Must cover every frequency from DC to GHz
    • Higher order harmonics for edge integrity
    • High number of critical signals
    • Digital signals more tolerant to distortion
    • Switching create high currents in short periods

Transmission Line

  • I/O channels: connection between chips
    • Low frequency: ideal equipotential net
    • High frequency: transmission line
      • Finite velocity of signal along wire
      • Characteristic impedance of wire

Transmission Line Effects

  • Occur when rise time is comparable to path delay
    • Reflections interfere with transitions
    • Can cause false/multiple switching
    • Use PCB layout to minimize effects

  • When is a wire a T-line
    • Propagation delay comparable to the edge rate of the signal
    • Depends on
      • Length
      • Speed of light in the medium
        • $$c = \frac{1}{\sqrt{\epsilon_0 \mu_0}}$$
        • Signal propagation velocity $$v = \frac{1}{\sqrt{\epsilon \mu}}$$
        • $$\frac{v}{c} = \sqrt{\frac{\epsilon_0 \mu_0}{\epsilon \mu}} \approx \sqrt{\frac{\epsilon_0}{\epsilon}}$$
        • $$\epsilon_0$$: permittivity in vacuum
        • $$\epsilon = k \epsilon_0$$: permittivity in a given medium
        • $$\mu_0$$: permeability in vacuum
        • $$\mu$$: permeability in a given medium
      • Edge rate

Characteristic Impedance

  • Transmitter cannot see what is connected at the receiver end, but only the load impedance
  • $$Z_0$$: ratio between voltage & current waves that travel down the channel
    • For uniform, lossless transmission line (no resistance, no dielectric loss):
      • $$Z_0 = \sqrt{\frac{L}{C}}$$
      • $$C$$: capacitance per unit length
      • $$L$$: inductance per unit length

Reflections

  • If load impedance != characteristic impedance, part of energy will reflect when a wave hits the end of a T-line
  • Reflection coefficient: $$\Gamma = \frac{Z_L - Z_0}{Z_L + Z_0}$$
  • Reflection wave of amplitude: $$V{reflected} = \Gamma V{incident}$$
  • Total wave = sum of incident & all reflected waves

Termination

  • Point-to-point links
    • Source termination
      • No ringing
      • No power dissipation in load -> save power
  • Multidrop busses
    • Load termination
      • No ringing
      • Power dissipation in load resistor
      • Ensure valid logic levels
  • Busses with multiple receivers & drivers
    • Terminate at both ends
      • Prevent reflections from either end

Matched Termination

Mismatched Termination

Open & Short Termination

  • Open circuit: $$\Gamma = 1$$
  • Short circuit: $$\Gamma = -1$$

Noise and Interference

Intersymbol Interference

  • Must wait until reflections damp out before sending next bit
  • Unterminated transmission line: minimum bit time = several round trips along the line
Dispersion
  • Nonzero line resistance

Crosstalk
  • Capacitance to neighbors
  • Noise on non-switching wires (by the neighbor switching wire)
  • Increased delay on switching wires (i.e. changing from 0/1 to 1/0)

  • If victim floating, model as capacitive voltage divider
    • $$\Delta V{victim} = \frac{C{adj}}{C{gnd-v} + C{adj}} \Delta V_{aggressor}$$

  • Usually victim driven by a gate that fights noise
    • Noise depends on relative resistances
    • Victim driver in linear region, aggressor in saturation
    • If sizes are same, $$R{aggressor} = (2-4) R{victim}$$
    • $$\Delta V{victim} = \frac{C{adj}}{C{gnd-v} + C{adj}} \frac{1}{1+k} \Delta V_{aggressor}$$
    • $$k = \frac{\tau{aggressor}}{\tau{victim}} = \frac{R{aggressor}(C{gnd-a} + C{adj})}{R{victim}(C{gnd-v}+C{adj})}$$

Ground Bounce
  • Nonzero return path impedance

Electrostatic Discharge (ESD) Protection

  • Static electricity builds up on your body
  • Must dissipate this shock energy before it reaches the gates, or else they may burn
  • ESD protection circuits
    • Current limiting resistor
    • Diode clamps
  • ESD testing
    • Views human as charged capacitor

High Speed Transmitter and Receiver

Transmit data faster than the flight time along the line.

Transmitter

Must generate very short pulses.

  • Termination?
    • High-impedance driver + load termination
    • Low-impedance driver + source termination
  • Single-ended v.s. differential
    • Single-ended
      • Uses half the wires
    • Differential
      • Represent signal with a difference between two voltages or currents
        • Flip the signal, send original + flipped, subtract at receiver side
        • Immune to common mode noise
  • Pull-only v.s. push-pull
    • Pull-only
      • Use 0 (no signal) as one of the signal levels
      • Half the transistors, easier design
    • Push-pull
      • Bipolar signals centered around 0
      • Uses less power for the same swing

Receiver

Must be accurately synchronized to detect the pulses.

Noise Implicatoins

  • If noise < noise margin, nothing happens
  • Static CMOS logic will eventually settle to correct output even if disturbed by large noise spikes
    • Glitches cause extra delay
    • False transitions cause extra power
  • Memories, sequential logic circuits, & other sensitive circuits never recover from glitches & wrong switching

Wire Engineering

  • Goal
    • Achieve delay, area, power goals with acceptable noise
  • Degrees of freedom
    • Width
    • Spacing
    • Layer
    • Shielding
Repeaters

An electronic device that receives a signal and retransmits it.

  • R & C proportional to $$l$$ -> RC delay proportional to $$l^2$$
    • Break long wires into N shorter segments, drive each one with a repeater
      • Repeater: inverter, buffer, ...

  • Design
    • How many repeaters?
    • How large should each one be?
    • Equivalent circuit
      • Wire length $$\frac{1}{N}$$
        • Wire capacitance $$C_W * \frac{1}{N}$$
        • Resistance $$R_W * \frac{1}{N}$$
      • Inverter width $$W$$
        • Gate capacitance $$C'*W$$
        • Resistance $$\frac{R}{W}$$
    • RC delay roughly proportional to $$\frac{l^2}{N}$$
          • repeater delay
          • power
  • Results
    • Elmore delay
      • Differentiate w.r.t. W and N
      • Set equal to 0, solve equations
        • Best length between repeaters: $$\frac{l}{N} = \sqrt{\frac{2RC'}{R_W C_W}}$$
        • Best delay per unit length: $$\frac{t_{pd}}{l} = (2+\sqrt{2})\sqrt{RC'R_WC_W}$$
        • Inverter size: $$W = \sqrt{\frac{R C_W}{R_W C'}}$$
    • Energy / length $$\approx 1.87 CW V{DD}^2$$
      • 87% premium over unrepeated wires
      • Extra power consumed in large repeaters
    • If repeaters downsized for minimum energy-delay-product (EDP)
      • Energy premium only 30%
      • Delay increases by 14% from min delay

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