Introduction
Some Definitions
- State: all information about a circuit necessary to explain its future behavior
- Latches & flip-flops: state elements storing 1 bit of state
- Synchronous sequential circuits: combinational logic followed by a bank of flip-flops
State Elements
| Bistable Circuit | SR Latch | D Latch | D Flip-Flop | |
|---|---|---|---|---|
| Input | N/A | S, R | D, CLK | D, CLK |
| Output | Q, ~Q | Q, ~Q | Q, ~Q | Q, ~Q |
| Gates | 2 NOT | 2 NOR | 1 SR Latch + 1 NOT + 2 AND | 2 D Latch + 1 NOT |
| Transistors (CMOS) | 4 | 8 | 22 | 46 |
| Pros | 2 stable states (1 bit of info), essential for sequential circuits to store memory | Inputs to control the state of the circuit | Avoid the invalid state with filter at front; separate "what" from "when" to change | Output change only allowed at CLK edge |
| Cons | No input, cannot control | Has invalid state (S = 1, R = 1); mix "what to change" with "when to change" | Output changes continuously when CLK = 1 -> but if the value goes back to the correct state before the falling edge of CLK, it should be fine? -> not affecting functionality, but waste energy! | H/W cost |
Bistable Circuit
Building block of other elements.
S/R Latch (Set/Reset)
Memory controllable. But has invalid state.
- S = 1
- Set
- R = 1
- Reset
- S = 0, R = 0
- Memory
- S = 1, R = 1
- Invalid
D Latch
Latches D to Q when CLK = 1; prevent invalid state.
- CLK = 0
- Keep state
- CLK = 1
- Latch D
D Flip-Flop
Only latches D to Q on rising clock edge.
- CLK = 0
- D to N1
- CLK = 1
- N1 to Q
D Latch v.s. D Flip-Flop
Register
Enabled Flip-Flop
- EN = 1
- D to Q on clock edge
- EN = 0
- Q remains
Resettable Flip-Flops
Reset = 1
Synchronous
- Q = 0 on clock edge
Asynchronous
- Q = 0 immediately
- Requires internal circuit change in D flip-flop
Reset = 0
- Normal D flip-flop
Settable Flip-Flop
- Set = 1
- Q = 1
- Set = 0
- Normal D flip-flop
Synchronous Sequential Logic Design
- Breaks cyclic paths by inserting registers
- Registers contain state of the system
- State changes at clock edge (synchronized)
- Rules
- Every circuit element either a register or combinational circuit
- At least one register
- All registers receive the same clock signal
- Every cyclic path at least one register
- Common synchronous sequential circuits
- Finite state machines
- Pipelines
Timing
- Setup time $$t_{setup}$$: time before clock edge D must be stable
- Hold time $$t_{hold}$$: time after clock edge D must remain stable
- Aperture time $$ta = t{setup} + t_{hold}$$
- During which circuit inputs must be stable
- Propagation delay $$t_{pcq}$$: time after clock edge Q is guaranteed to be stable i.e. stop changing
- Contamination delay $$t_{ccq}$$: time after clock edge Q might be unstable i.e. start changing
Dynamic Discipline
Setup Time Constraint
- $$t_{pd}$$
- Useful work, don't wanna sacrifice this
- $$T_C$$
- Increase clock time, decrease performance
Hold Time Constraint
- $$t_{cd}$$
- Make your combinational circuit slower (changing circuit design) -> painful, but only resort
Setup Time Constraint with Skew
Worst case: CLK2 earlier than CLK1
Hold Time Constraint with Skew
Worst case: CLK2 later than CLK1
Violating Dynamic Discipline
e.g. asynchronous inputs
Metastability
- Bistable devices: 2 stable states, 1 metastable state in between
- If land in metastable state, could stay there for an arbitrary amount of time
- Probability that Q is metastable after waiting some time
- $$P(t_{res} > t) = \frac{T_0}{T_C} e^{-\frac{t}{\tau}}$$
- $$t_{res}$$time to resolve to 0/1
- $$T_0$$: aperture window
- $$\tau$$: time constant for how fast flip-flop moves away from metastability (dependent on R, C, gain of buffer G, etc.)
- $$t$$ increases, probability decreases, resolve to stable states
Synchronizer
- Mean Time Between Failure (MTBF)
- $$P(failure)/second = \frac{NT0}{T_C} e^{-\frac{(t_C - t{setup})}{\tau}}$$
- $$MTBF = \frac{1}{P(failure)/second} = \frac{TC}{NT_0} e^{\frac{(t_C - t{setup})}{\tau}}$$
- $$N$$: input changes $$N$$ times per second