Content

1. Overview
2. Memory Technologies
   1. Types of Memory
   2. DRAM
      1. Operations
      2. Performance
   3. SRAM
      1. Performance
3. Memory Hierarchy

Overview

• Challenges
  • Capacity
  • Performance
    • Latency
    • Bandwidth
• Solution
  • Memory hierarchy

Memory Technologies

Types of Memory

DRAM

• Data stored in single capacitor
• Read/write access through transistor (1T cell)
• Read destructive
  • Write back after read
• Charge leakage
  • Refresh

• Interleaved memory: 4-8 logical banks on each chip
  • Increase throughput

Operations

1. Precharge bit lines to Vdd/2
2. Row access
   • Enable target word line
     • 1: V_bitline up
     • 0: V_bitline down
   • Sense amps sense changes in bitline voltage & latch results
     • Small voltage change because charge stored in a small cap is shared with long bitline
     • Sense amps restore data; or write data into sense amp latches
3. Column access: select desired output from output latch

Performance

• High latency on the first bit: each step takes 15-20 ns
• High bandwidth on subsequent accesses
  • Burst mode
  • Synchronous DRAM
  • Double data rate interface
• High capacity

SRAM

• Data stored based on standard digital circuit
• Simple read/write interface
• Smaller capacity

Performance

• Low latency
• Deterministic latency: no refresh
• Low capacity: 6T SRAM cell
• Can be fabricated in the same logic IC process
  • Same die as CPU

Memory Hierarchy